Method for fabricating semiconductor memory device

ABSTRACT

A semiconductor memory device is provided which prevents a lifting phenomenon by improving an adhesive strength between an upper electrode and an interlayer insulating layer. The semiconductor memory device includes a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode; an adhesion layer formed on the upper -electrode; an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor memory deviceand, more particularly, to a method for fabricating a semiconductormemory device, in which a lifting phenomenon is prevented by improvingan adhesive strength between an upper electrode and an interlayerinsulating layer.

DESCRIPTION OF THE PRIOR ART

[0002] With the recent progress in film deposition techniques,applications of a nonvolatile memory cell using a ferroelectric thinfilm have increasingly been developed. This nonvolatile memory cell is ahigh-speed rewritable nonvolatile memory cell utilizing the high-speedpolarization/inversion and the residual polarization of theferroelectric capacitor thin film.

[0003] Therefore, a ferroelectric random access memory (FeRAM) where acapacitor thin film with ferroelectric properties such as strontiumbismuth tantalate (SBT) and lead zirconate titanate (PZT) isincreasingly used for a capacitor, because it assures a low-voltage andhigh-speed performance, and does not require periodic refresh to preventloss of information during standby intervals like a dynamic randomaccess memory (DRAM).

[0004] Since a ferroelectric material has a dielectric constant rangingfrom a value of hundreds to thousands and a stabilized residualpolarization property at room temperature, it is being applied to thenon-volatile memory-device as the capacitor thin film. When employingthe ferroelectric capacitor thin film in the non-volatile memory device,information data are stored by polarization of dipoles when electricfield is applied thereto. Even if the electric field is removed, theresidual polarization still remains so that the information data, i.e.,“0” or “1”, can be stored.

[0005] In fabricating a ferroelectric capacitor, a high-temperaturethermal treatment is carried out so that a lower/upper electrode isformed using Pt, Ir, Ru, their oxides or a combination thereof. However,since these materials have poor adhesive characteristics, a liftingphenomenon occurs during a following thermal treatment. The liftingphenomenon can be prevented by forming an adhesion layer between a lowerelectrode and an interlayer insulating layer.

[0006] Meanwhile, there is no adhesion layer between an upper electrodeand an interlayer insulating layer covering the upper electrode. As aresult, during a cleaning process after a formation of a contact holeexposing the upper electrode, a cleaning solution soaks into a boundarybetween the upper electrode and the interlayer insulating layer, so thata lifting phenomenon results.

SUMMARY OF THE INVENTION

[0007] It is, therefore, an object of the present invention to provide amethod for fabricating a semiconductor memory device, in which theoccurrence of a lifting phenomenon is prevented by improving an adhesivestrength between an, upper electrode and an interlayer insulating layer.

[0008] In accordance with an aspect of the present invention, there isprovided a semiconductor memory device, comprising a capacitor formed ona semiconductor substrate, wherein the capacitor includes a lowerelectrode, a dielectric layer and an upper electrode; an adhesion layerformed on the upper electrode; an interlayer insulating layer coveringthe capacitor, wherein a portion of the interlayer insulating layer isin contact with the adhesion layer; a contact hole, formed within theinterlayer insulating layer, whose bottom exposes the upper electrodeand whose sidewalls expose the interlayer insulating layer and theadhesion layer; and an interconnection line coupled to the capacitor viathe contact hole.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other objects and aspects of the invention will become apparentfrom the following description of the embodiments with reference to theaccompanying drawings, in which:

[0010] FIGS. 1 to 4 are cross-sectional views illustrating sequentialsteps of a FeRAM in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIGS. 1 to 4 are cross-sectional views illustrating sequentialsteps of a FeRAM in accordance with the present invention.

[0012] Referring to FIG. 1, an interlayer insulating layer 11 is formedon a semiconductor structure 10 that includes transistors formed on thesemiconductor substrate 10. Then, a lower adhesion layer 12, a lowerelectrode layer 13, a ferroelectric layer 14, an upper electrode layer15, an upper adhesion layer 16 and a hard mask layer 17 are sequentiallyformed on the interlayer insulating layer 11.

[0013] At this time, the upper adhesion layer 16 can be formed withmaterial such as Ti, Ta, Zr, Hf or the like, which acquires adhesioncharacteristic by oxidation of the materials during a thermal treatmentfor recovering a ferroelectric characteristic. The upper adhesion layer16 can be also formed with TiO₂, Ta₂O₅, ZrO₂, HfO₂, or the like.

[0014] The upper adhesion layer 16 is formed by using several methodssuch as physical vapor deposition (PVD), a chemical vapor deposition(CVD), an atomic layer deposition (ALD) and an electrochemicaldeposition (ECD) . It is preferable to form the upper adhesion layer 16to a thickness of 50 Å to 500 Å. Meanwhile, the upper electrode layer 15can be formed with Pt, Ir, Ru, their oxides, or a combination thereof,and the hard mask layer 17 can be formed with TiN, TaN or WN.

[0015] Referring to FIG. 2, the hard mask layer 17 is patterned to forma patterned hard mask layer (not shown), and the upper electrode layer15 is etched by using the patterned hard mask layer as an etching maskto thereby form an upper electrode pattern 15A. Then, the patterned hardmask layer is removed to expose the upper adhesion layer 16A.Thereafter, the ferroelectric layer 14 and the lower electrode layer 13are patterned to form a patterned ferroelectric layer 14A and apatterned lower electrode layer 13A.

[0016] Referring to FIG. 3, a thermal treatment for recovering)adegraded ferroelectric characteristic is carried out. At this time, theupper adhesion layer 16A is oxidized to thereby form an adhesive oxidelayer 16B. The thermal treatment is carried out at an oxygen atmosphereunder a temperature of 300° C. to 1000° C. Preferably, before or afterthe thermal treatment, a plasma process, an ozone process or a rapidthermal process can be carried out in order to enhance the oxidation.

[0017] Referring to FIG. 4, an interlayer insulating layer 18 is formedon the entire structure. Then, the interlayer insulating layer 18 andthe adhesive oxide layer 16B are selectively etched to form a contacthole, whose bottom exposes the upper electrode layer 15A and whosesidewalls expose the interlayer insulating 18 and the adhesive oxidelayer 16B.

[0018] The foregoing procedure may be performed by using a typicalmethod for fabricating the FeRAM.

[0019] Since the FeRAM-in accordance with the present invention has anadhesion layer between the upper electrode and the interlayer insulatinglayer, a cleaning solution does not soak into a boundary between theupper electrode and the interlayer insulating layer so that a liftingphenomenon is prevented. Additionally, since it is possible to perform acleaning process by using a strong cleaning solution, a low contactresistance can be obtained.

[0020] Although the preferred embodiments of the invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

What is claimed is:
 1. A semiconductor memory device, comprising: acapacitor formed on a semiconductor substrate, wherein the capacitorincludes a lower electrode, a dielectric layer and an upper electrode;an adhesion layer formed on the upper electrode; an interlayerinsulating layer covering the capacitor, wherein a portion of theinterlayer insulating layer is in contact with the adhesion layer; and acontact hole, formed within the interlayer insulating layer, whosebottom exposes the upper electrode and whose sidewalls expose theinterlayer insulating layer and the adhesion layer.
 2. The semiconductormemory device as recited in claim 1, wherein the adhesion layer isformed with a material selected from the group consisting of Ti, Ta, Zr,Hf, TiO₂, Ta₂O₅, ZrO₂ and HfO₂.
 3. The semiconductor memory device asrecited in claim 2, wherein the dielectric layer is a ferroelectriclayer.
 4. A method for fabricating a semiconductor memory device,comprising steps of: a) forming a capacitor by stacking a lowerelectrode, a dielectric layer and an upper electrode on a semiconductorsubstrate; b) forming an adhesion layer and a hard mask layer on theupper electrode; c) etching the adhesion layer and the upper electrodeby using the hard mask layer as an etching mask; d) removing the hardmask layer to expose the adhesion layer; e) patterning the dielectriclayer and the lower electrode; f) forming an interlayer insulating layeron an entire structure to bring a portion of the interlayer insulatinglayer into contact with the adhesion layer; and g) selectively etchingthe interlayer insulating layer and the adhesion layer to form a contacthole, a bottom of said contact hole exposing the upper electrode andsidewalls of said contact hole exposing the interlayer insulating layerand the adhesion layer.
 5. The method as recited in claim 4, wherein thedielectric layer is a ferroelectric layer.
 6. The method as recited inclaim 5, further comprising, after the step e), a step of carrying out athermal treatment at an oxygen atmosphere.
 7. The method as recited inclaim 4, wherein the adhesion layer is formed with a material selectedfrom the group consisting of TiO₂, Ta₂,O₅, ZrO₂ and HfO₂.
 8. The methodas recited in claim 7, further comprising, after the step e), a step ofcarrying out one of a rapid thermal process, a plasma process and anozone process.